In high speed signal circuitry such as transmitters which might be used with serial interfaces, it is desirable to have controlled rise/fall times for output transitions. Very fast transitions cause EMI (Electro Magnetic Interference) and very slow transitions result in poor receiver performance.
The rise and fall times at the transmitter pad are determined by: the output impedance of the driver, the characteristic impedance of the transmission line and the total lumped capacitance on the pad. The rise and fall times can be represented by simple RC charge and discharge. (Herein, the word capacitance is written abbreviated sometimes as “cap”).
FIG. 1 shows a prior art type of current mode driver and a voltage mode driver in the context of a transmitter pad. It is noted in the context of FIG. 1 that the rise-fall times, as shown by way of example are first order RC.
The output impedance of the driver of the transmitter is generally matched with the characteristic impedance of the line, for design purposes. The value of each impedance is determined by factors such as transmission line design, output voltage swing, and dc power consumption. Typically and as an example, both the impedances may be of the order of 50 Ohms. In some cases they may be of the order of 100 Ohms. In some current mode drivers, the termination impedance may be chosen to be much larger than the line impedance, in order to save power. The transitions are still an RC phenomenon, but they are now controlled by the line impedance more than the transmitter termination impedance.
Once the line impedance is known, the total capacitance on the pad is one parameter with which to control the rise and fall times. In some applications, especially at high data rates, it is desirable to keep the pad capacitance to a minimum so as to prevent reflections at high frequencies. In such cases the rise/fall times become very small, and a method is required to increase the transition times. In some other applications, there might be too much pad capacitance on the pads, owing to high-capacitance ESD structures or the self-capacitance of other transmitters and receivers sharing the same pads. In such cases, the rise/fall times are very large and the transition times need to be reduced.
In prior art, often short duration current pulses (lasting a fraction of the transition time, for example) are used to either slow down or speed up transitions. In known art, current sources provide extra charge which helps either to speed up or slow down the transition. Such a prior art scheme is shown in FIG. 2. There are two disadvantages to the prior art scheme shown in FIG. 2. First, the width of the current pulse needs to be controlled. This implies generating an accurate timing which is a small fraction of the data rate itself, which is a difficult and jitter-prone proposition at high data rates. Second, for low voltage swing, low common mode applications (and these are becoming increasingly popular) the current sources which sink current (I_2 and I_4) will not have enough voltage headroom.
A design example addressing the problems referenced in the previous paragraphs is presented in the present and the next paragraph in the context of MIPI D-PHY standard. As known, MIPI D-PHY standard is a PHY standard for serial interfaces used in mobile phones. Examples of such include camera and display system applications conveying data between the cell phone processor chip and display or camera chips. MIPI D-PHY standard requires a voltage mode driver with 50 Ohm single-ended impedance. The common-mode is 200 mV and the differential swing is ±100 mV on top of the common mode. Stringent high-frequency reflection requirements translate to a max capacitance limit on the pad=1.5 pF (see FIG. 3). The minimum rise time (20% to 80% of dc value) allowed is 150 ps. A simple RC across process variation gives the worst case, minimum rise time of 70 ps. In such a case, the nominal value of time constant=(50∥50)*1.5 pf=30 ps and around two time constants are required for a 20%-80% charging. Hence a scheme to slow-down transmission times is required.
FIG. 3 is a design example addressing problems referenced above and illustrates a MIPI D-PHY transmitter showing the line state when the transmitter is driving a differential ‘1’. The voltage levels, with 100 mV minimum, offer too less of a voltage head-room with which to design low capacitance current sources. The scheme based on current pulses will be difficult to design. Also, generating accurate pulses with width in 10 s of pico-seconds is a difficult and costly proposition.
An improved scheme is required to control transmitter rise-fall times for a serial interface without requiring additional timing or dedicated additional current pulses. Such improved scheme also needs to work for low common mode, low differential swing applications.